1. Field of the Invention
The present invention generally relates to testing of integrated circuits and more, specifically, to a clock controller for use in at-speed testing of scan circuits.
2. Description of Related Art
Scan circuits are well known and generally consist of logic and scan chains comprised of memory elements which can be configured in a scan mode and a capture mode. The scan mode is used for shifting test patterns into the memory elements and for shifting the circuit response to the test patterns out of the memory elements. The capture mode is used to capture and store the response of the circuit in the memory elements.
An at-speed test is typically performed by applying a short burst of two clock cycles to launch the test pattern shifted in and capture the output response of the circuit. In some cases, the launching is performed while the memory elements of the circuit are configured in shift mode (launch-from-shift), while in other cases, the memory elements are configured in capture mode (launch-from-capture). Short bursts are not appropriate to test for complex failure mechanisms such as power supply noise, IR-drop, signal coupling, etc . . . and longer bursts need to be used. Ideally, the level of activity of the circuit during the burst phase should approximate that which occurs during normal operation of the circuit. This can be achieved by modifying the burst length and/or the instantaneous frequency of the burst. For interacting synchronous domains, an additional characteristic is the alignment of selected clock edges during the burst.
Lackey U.S. Pat. No. 6,467,044 issued on Oct. 15, 2002 for “On-board Clock-control Templates for Testing Integrated Circuits” is concerned with problems associated with testing integrated circuits having multiple clock domains. More specifically, Lackey is concerned with a clocking methodology that will generate clock waveforms for all clock domains from a single clock. Lackey provides templates in the form of registers containing bits that enable/disable the capture clock(s), to provide for maximum flexibility in describing clock waveforms. The approach proposed by Lackey suffers from a number of disadvantages. The size of the registers become prohibitive for long burst lengths. The patent does not disclose how to perform an at-speed test of all clock domains at the same time if the clocks are not multiples of each other because all capture clocks are derived from a single capture clock source. Further, the patent does not specifically address how to handle interacting synchronous clock domains and the disclosed method applies only to the Level Sensitive Scan Design (LSSD) style. The muxed-scan design style is more commonly used. The clocked-scan design styles is also used in high-performance designs.